MULTI_BLK_SEL=Val_0x0, BLOCK_COUNT_ENABLE=Val_0x0, RESP_INT_DISABLE=Val_0x0, RESP_ERR_CHK_ENABLE=Val_0x0, RESP_TYPE=Val_0x0, AUTO_CMD_ENABLE=Val_0x0, DATA_XFER_DIR=Val_0x0, DMA_ENABLE=Val_0x0
Transfer Mode Register
| DMA_ENABLE | DMA Enable. This bit enables the DMA functionality. If this bit is set to 0x1, a DMA operation begins when the Host Driver writes to the SDMMC_CMD_R register. One of the DMA modes can be selected by setting the SDMMC_HOST_CTRL1_R[DMA_SEL] bit field. 0 (Val_0x0): No data transfer or non-DMA data transfer 1 (Val_0x1): DMA data transfer |
| BLOCK_COUNT_ENABLE | Block Count Enable. This bit is used to enable the SDMMC_BLOCKCOUNT_R register, which is relevant for multiple block transfers. If this bit is set to 0x0, the SDMMC_BLOCKCOUNT_R register is disabled, which is useful in executing an infinite transfer. The Host Driver must set this bit to 0x0 when ADMA is used. 0 (Val_0x0): Disable 1 (Val_0x1): Enable |
| AUTO_CMD_ENABLE | Auto Command Enable. This bit field determines use of Auto Command functions. 0 (Val_0x0): Auto Command disabled 1 (Val_0x1): Auto CMD12 enable 2 (Val_0x2): Auto CMD23 enable 3 (Val_0x3): Auto CMD Auto select |
| DATA_XFER_DIR | Data Transfer Direction Select. This bit defines the direction of the DAT line data transfers. This bit is set to 0x1 by the Host Driver to transfer data from the SD or eMMC card to the Host Controller and it is set to 0x0 for all other commands. 0 (Val_0x0): Write (Host to Card) 1 (Val_0x1): Read (Card to Host) |
| MULTI_BLK_SEL | Multi/Single Block Select. This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0x0, it is not necessary to set the SDMMC_BLOCKCOUNT_R register. 0 (Val_0x0): Single block 1 (Val_0x1): Multiple block |
| RESP_TYPE | Response Type R1/R5. This bit selects either R1 or R5 as a response type when the Response Error Check is selected (SDMMC_XFER_MODE_R[RESP_ERR_CHK_ENABLE]). Error statuses checked in R1:
0 (Val_0x0): R1 (Memory) 1 (Val_0x1): R5 (SDIO) |
| RESP_ERR_CHK_ENABLE | Response Error Check Enable. The Host Controller supports response check function to avoid overhead of response error check by the Host Driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller checks the response error, this bit and the SDMMC_XFER_MODE_R[RESP_INT_DISABLE] bit should be set to 0x1. If an error is detected, the Response Error interrupt is generated (see SDMMC_ERROR_INT_STAT_R[RESP_ERR] bit). Note: Response error check must not be enabled for any response types other than R1 and R5. 0 (Val_0x0): Response Error Check is disabled 1 (Val_0x1): Response Error Check is enabled |
| RESP_INT_DISABLE | Response Interrupt Disable. The Host Controller supports response check function to avoid overhead of response error check by the Host Driver. Response types of only R1 and R5 can be checked by the Host Controller. If the Host Driver checks the response error, this bit should be set to 0x0 and wait for Command Complete interrupt and then check the respective response register (SDMMC_RESP01_R, SDMMC_RESP23_R, SDMMC_RESP45_R, and SDMMC_RESP67_R). If the Host Controller checks the response error, this bit and the SDMMC_XFER_MODE_R[RESP_ERR_CHK_ENABLE] bit should be set to 0x1. The Command Complete interrupt is disabled by this bit regardless of the Command Complete Signal Enable (SDMMC_NORMAL_INT_SIGNAL_EN_R[CMD_COMPLETE_SIGNAL_EN]). 0 (Val_0x0): Response interrupt is enabled 1 (Val_0x1): Response interrupt is disabled |